Method for optimizing the characteristics of integrated circuits components from circuit specifications

ABSTRACT

A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

This application claims the benefit of U.S. Provisional Application No.60/240,882, filed Oct. 17, 2000.

FIELD OF THE INVENTION

The present invention pertains to the optimization of the performanceand manufacturability of integrated circuits.

BACKGROUND OF THE INVENTION

The vertiginous growth of the micro-electronics market has created a setof spectacular problems both from technical and from the business pointof view. The investment required to set up a Very Large Scale ofIntegration (VLSI) fabrication plant for Deep Sub-Micron (DSM)technologies is in excess of 1 Billion U.S. dollars, and the time tocapitalize on that investment is constantly shortening; the speed andpower performance capabilities of consumer products and technologies,such as telecommunications, networking, entertainment, and the likebecome obsolete rapidly and need to be constantly improved.

Therefore, it is desirable for any IC foundry to be able to servemutliple end-user applications with the same fabrication technology, inorder to achieve consistent economy of scale saving.

The problem of modeling and optimizing the electrical properties ofintegrated devices has been recently explored in the work of M. Miyamaand S. Kamohara “Circuit Performance Oriented Device Optimization usingBSIM3 Pre-Silicon Model Parameters”, IEEE-ACM Asia-Pacific DAC,Yokohama, JP, January 2000, where the predictive capabilites of standardBsim3v3 SPICE model have been applied towards modeling and optimizationof the critical path of a CPU. SPICE (Simulation Program with IntegratedCircuit Emphasis) is a family of programs (freeware or commercial) forsimulation of electronic circuits, based on a kernel developed byBerkeley University (California, USA) since 1960 with public founds.Today's commercial packages are based on SPICE3f5, and they add to itmany functions and features.

In these methods, the target circuits are directly simulated using theSPICE program while manually changing the value of the Bsim3v3 modelparameters until the desired specifications are met. This procedure ishighly inefficient.

In another recent publication (Y. Cao, T. Sato, M. Orshansky, D.Sylvester and C. Hu, “New Paradigm of Predictive MOSFET and InterconnectModeling for Early Circuit Simulation”, IEEE 2000 Custom IntegratedCircuits Conference, Orlando (Fla.), May 2000) the problem of generatingpredictive SPICE model parameters is also addressed by using the Bsim3v3standard MOSFET model.

However, different product applications pose different, sometimesconflicting, requirements on the underlying technology components, andthe specification of a complete set of device characteristics (such as,for example, MOSFETs threshold voltage and drive current (I_(DS)),trans-conductance (g_(m)), output conductance (g_(ds)) and the like,which best fit that large set of multiple, conflicting requirements) isan overwhelming task using the methods and systems of the prior art.

SUMMARY OF THE INVENTION

One aspect of the invention is a method for selecting a process forforming a device, comprises generating a plurality of equations using aresponse surface methodology model. Each equation relates a respectivedevice simulator input parameter to a respective combination ofprocessing parameters that can be used to form the device. A model of afigure-of-merit circuit is formed that is representative of anintegrated circuit into which the device is to be incorporated. One ofthe combinations of processing parameters is identified that results ina device satisfying a set of performance specifications for thefigure-of-merit circuit, using the plurality of equations and the devicesimulator.

Another aspect of the invention is a method for designing a device,comprising generating a plurality of equations using a response surfacemethodology model. Each equation relates a respective device simulatorinput parameter to a respective combination of device characteristics. Amodel of a figure-of-merit circuit is formed that is representative ofan integrated circuit into which the device is to be incorporated; andidentifying one of the combinations of device characteristics thatcauses the device to satisfy a set of performance specifications for thefigure-of-merit circuit, using the plurality of equations and the devicesimulator.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram showing an exemplary method according to thepresent invention.

OVERVIEW

The exemplary embodiment of the invention is an efficient method foroptimizing the characteristics of devices, such as MOSFETs and BJTtransistors, Capacitors, Resistors and the like, for the types ofIntegrated Circuits (ICs) in which they are incorporated. In theexemplary method, a set of Figure Of Merit (FOM) circuits are designedin order to extract the sensitivity of circuit performance parameters tothe characteristics of the constituent devices that are to be optimized.A set of performance objectives and constraints are defined for the FOMcircuit performance parameters, and the device characteristics areoptimized in order to maximize the performance objectives while meetingall the constraints. In this way, it is possible to quickly andeffectively tune the devices of any given IC fabrication technologyaccording to application specific requirements, such as high speed,low-power, or analog.

The exemplary system explicitly models the target circuit performance(CPU critical path delay) as a function of physical process parameters.This allows optimization of the device based on the circuitspecification of a circuit that includes the device. Preferably, themethod uses data characterizing the device derived from two differentsources: (1) empirically measured current v. voltage (IV) andcapacitance v. voltage (CV) data taken from actual circuits, and (2)expanded (parameterized) SPICE models derived by inverse modeling basedon the IV-CV data. These two data flows are combined at the level of theparameterized SPICE models.

The exemplary method shown in FIG. 1 includes the following four steps:

1. Steps 125 and 130 form parametrized compact device models, in whichthe variables of the models are functions of the physical devicecharacteristics. This is accomplished by running a Design Of Experiments(DOE) on a set of device variables, such as energy and dose for channelimplants, source/drain implants, and the like, extracting the value ofthe parameters of the compact device model for all points of the DOE atstep 125 and fitting a low order polynomial model to the values byinverse modeling at step 115.

2. At step 140 a set of Figure Of Merit circuits is selected.

3. At step 135, the performance parameters of the FOM circuits areevaluated for all the points of the DOE defined in step 1 and a ResponseSurface Methodology (RSM) Model is constructed.

4. At step 160, the RSM macro-models are optimized according to a set ofperformance objectives and specifications. The AC/DC devicecharacteristics 155 corresponding to the optimum device are extractedand used to derive a set of specifications for the design of the deviceat step 165.

DETAILED DESCRIPTION

The exemplary approach constructs a direct mapping between theintegrated circuit device space and the integrated circuit performancespace to analyze and quantify the impact of device design on circuitdesign. The relationship between devices and the end-of-line circuit istypically broken into two direct mappings; the first being a compactmodeling of the device by fitting simulated and/or measuredcharacteristics and the second by the fitted compact model parameters tothe circuit via simulation tools such as SPICE style integrated circuitsimulators. Circuit response by this typical formulation can only berelated to the device compact model and relies heavily on the accuracyof the physics employed by such a model to infer the responses relationto the original device structure and its characteristics. The methoddescribed herein allows a direct relation between the componentstructure and its associated characteristics and the circuit response. Amapping as described allows optimization of an integrated circuit deviceby quantifying the tradeoffs in circuit response as a result ofexploring the component design space.

Compact Device Model Selection

One aspect of this method is the independence of the compact modelchosen to fit the simulated or measured device characteristics. Becausecompact models typically rely on both a physical and empirical set ofparameters to allow robust application over a wide range ofsemiconductor technologies, their direct representation of the actualdevice becomes corrupted at the expense of a better characteristic fit.The method of parameterizing the model in terms of the actual devicestructure is advantageous in that it decomposes this mostly non-physicalrepresentation into a representation which can be physically related tothe device under design. Such a decomposition does not rely upon theoriginal quality of the device compact model.

Initial Device Compact Model Extraction

The initial device compact model representation is carried out in afashion typical for device characteristic extraction. The nominal ortypical device is simulated or measured, providing its characteristics(e.g. IV-CV data) 110. At step 115, inverse modeling builds a devicestructure having characteristics that ideally exactly reproduce the data110. However, the characteristics are likely to differ slightly due toerrors introduced by inverse modeling 115. Therefore, as part of step115, a design of experiment (DOE) is run to generate many sets of“simulated” IV-CV data, from which each set is used to extract anindividual SPICE model 125. The inverse modeling creates an initial(inverse modeled) device structure 120. Ideally, the initial devicecharacteristics 110 are centered around the device parameter space suchthat exploring the space in one or multiple dimensions would require theleast perturbation in the original model fitting. This insures the mostaccurate mapping over the device space. This initial structure 120 has aDOE performed on it which creates the data for SPICE model extraction125. SPICE model extraction 125 then creates the data for building ofthe RSM model. At step 125, the data are fit to the parameter setcontained within the compact model of choice.

Device Model Parameterization

Parameterization of the device compact model entails performing a designof experiments over the device space. Each resulting experimental devicehas associated with it a corresponding set of device characteristicswhich may be extracted and fit to the same compact model used in theinitial compact model extraction. At least two methods exist which maybe utilized to perform this function. They are described as follows;

Inverse Modeling (step 115)

The physical device parameters (e.g. channel implant energy/dose, oxidethickness, LDD spacer, and the like) are perturbed per the defineddesign of experiments. Each resulting set of characteristics is fit tothe chosen device compact model.

Silicon Based Modeling

A design of experiments is applied as a set of split lot conditionswhich are defined to effectively perturb the equivalent devicestructural parameters as explained above. Each device is then measuredin silicon to extract the corresponding device characteristics resultingin the extraction of representative device compact model for each splitlot condition.

Response Surface Methodology (RSM) modeling is performed within step130. The SPICE model parameterization is representing the SPICE modelparameters by an RSM model instead of a constant parameter value.

Compact Model Expansion

At step 130, the design of experiments explained above results in a setof device compact model parameters for each device characteristicextraction. From the correlation information obtained by relating thedevice compact model parameter sets to their corresponding devicestructure perturbations, a first order decomposition of the underlyingdevice compact model equations may be performed such that the compactmodel parameters are equated to a linear function of the devicestructural parameters. This effectively maps the device structuralparameters to the compact model and retains the underlying physicsinherent to the device characteristics. Instead of merely specifyingmeasured parameters, equations are used to define how the SPICE modelparameters vary as a function of the process parameters used in formingthe devices. These expanded models are referred to as “parameterizedSPICE models”, wherein a respective equation is provided to specify eachrespective SPICE input parameter, as a function of input processes.

These equations are the RSM models provided within the inverse modelingblock 115. Now, the SPICE parameters can be a function of processingcondition parameters, or device architecture parameters. The parametersare decided upon based upon what is available to drive the DOE in step115. It is mainly a function of the tool used. In the exemplary method,device architecture parameters are used.

Figure of Merit Circuit Selection

At step 140, the Figure of Merit circuit selection is performed. Thecircuits in the FOM library are preferably simple, canonical circuitsthat capture the capability of a technology for a particular class ofapplications. The simplest example of a FOM circuit suitable forhigh-speed digital applications is a ring-oscillator. The propagationdelay (T_(pd)) of a ring-oscillator is representative of high speeddigital circuits. An example for capturing analog characteristics is abasic operational transconductance amplifier (OTA) circuit. An OTAexploits the effects of device characteristics in the strong inversionregions of operation (e.g. gds, gm) as opposed to those represented bytypical digital blocks. The robustness of this method allows a widerange of applications such as Analog/Mixed-Signal and DRAM to becharacterized in the same device structural space. Hence, tradeoffstowards one application or another may be quantified.

Device to Circuit Mapping

At step 135, the actual output response of the circuit based upon thedevice parameters may now be performed using the Figure of Meritcircuits in conjunction with the expanded device compact model(parameterized SPICE model). Typical circuit simulation is carried outon the Figure of Merit circuits to which the circuit response space isexplored via a Design of Experiments on the input device parameters.This effectively maps the device space directly to the circuit responsespace. The mapping is captured by the most accurate and capable modelfit allowed by the pre-defined DOE. Typical fits include linear,quadratic, cubic, and the like. Linear fits are not recommended due tothe inherent non-linear relationship between integrated circuit devicesand their applied circuit responses. The resulting representation of themapping is incorporated using response surface methods and exists as ananalytical model.

RSM Model Optimization

RSM based optimization relies upon the desired circuit responsesidentified as specifications for as many Figure of Merit circuits and/orstandard device characteristics (e.g. Vtsat, Idsat, and the like) asneeded. A global optimization is performed to satisfy the multipleconstraints given by the circuit specifications. The specifications aredriven either by an application specific set of objectives or a generalset intending to equalize the application of a particular technology tomultiple applications.

Obtaining the Optimal Device

Feeding back the results of optimizing the device in the circuitresponse space is accomplished by one of two methods. Each method hasits advantages. Each is described below;

Device Parameter Back-annotation (step 146)

This step is indicated by the dashed line 146 in FIG. 1. The optimizedanalytical representation of the circuit responses results in afinalized parameter set. This parameter set defines the inputs to theoriginal device structure from which the space was originally defined.Therefore, the parameters may be directly applied to the device foroptimization. The accuracy of back-annotation relies heavily on thequality of fit of the expanded device compact model (parameterized SPICEmodel).

Inverse Modeling (step 160)

Instead of device parameter back annotation, the optimized analyticalrepresentation of the circuit responses directly correlate the circuitperformances to the original device parameterization via the expandeddevice compact models (parameterized SPICE model). In one embodiment,between the two sets of IV-CV data 110 and 155, one set of data isobtained directly from experiments using actual devices, and the otherset of data is obtained through simulation. Preferably, IV-CV data 110are obtained empirically from experiments in silicon, and IV-CV data 155are provided from simulation. Alternatively, it is contemplated thatIV-CV data 110 may be obtained from simulations, and IV-CV data 155 maybe obtained empirically from experiments.

The actual output of such an optimization is a parameter set which isevaluated by the expanded device compact model (parameterized SPICEmodel). Evaluating this model for its representative devicecharacteristics 155 results in data applicable to a direct inversemodeling step 160 which results in a fitted device architecture 165matching the characteristics 155 generated by the optimization. Theaccuracy of inverse modeling 160 allows leniency in the accuracy of theexpanded device compact model (parameterized SPICE model) in that thefinal device structure fits the optimized device characteristics 155 (asdetermined by the capability of the inverse modeling methodology used).

Using device architecture parameters provides an initial devicestructure 120 and a final device structure 165, where the “final”structure has optimized performance. Then, an additional step (notautomated) is performed to determine how to implement the changes inexisting semiconductor process to achieve the final optimized structurein manufacturing.

Alternatively, if the DOE in step 115 is performed as a function ofprocessing condition parameters, then following generation of the finaldevice structure 165, this final step (of determining the appropriatechanges in fabrication process to implement the final device structure)is automated, and the optimized final structure is fabricated byimplementing these process changes.

The exemplary method may be practiced by utilizing the Circuit Surferstatistical design and verification environment (a yield-analysis andimprovement solution for analog and mixed-signal IC designers availablefrom Cadence Design Systems, Inc., of San Jose, Calif.) and the DeviceDesigner device analysis and optimization environment. The CircuitSurfer environment supports many tasks typically required for analog andmixed-signal design for manufacturability, such as statisticalsimulation, sensitivity analysis, response surface modeling, and circuitoptimization. Alternatively, another package capable of performingresponse surface methodology modeling may be used.

The device to circuit mapping is achieved within the framework byperforming a DOE over the device parameter space and modeling theresponse using quadratic RSM models. The Device Designer environmentsupports the exploration of the device architecture space byincorporating the ability to perform inverse modeling on a set of devicecharacteristic curves resulting in an equivalent representative devicestructure.

An exemplary method for optimizing the characteristics of IntegratedCircuit's devices, such as MOSFETs, BJTs, Capacitors, resistors and thelike for application specific purposes, such as but not limited tohigh-speed, low-power, high-gain, high-precision, low-noise etc, maycomprise the following steps.

1. Select a compact device model, for example Bsim3v3 (available fromthe Worldwide Web at the following uniform resource locator:http://www-device.EECS.Berkeley.EDU/˜bsim3) for MOSFETs devices, whichis available from the the University of California at Berkeley, Calif.There are many other commercial and public domain versions of SPICE thatare equally acceptable for this purpose.

2. Fully characterize the value of the compact model variables that bestfit the initial or nominal device characteristics 110, as obtained forexample, from direct measurements or simulations.

3. Run a Design Of Experiments (DOE) on the device parameters at step125 to extract their effect on the device output characteristics. Thisstep can be performed in two different ways.

In a variant of the exemplary embodiment, the DOE includes inversemodeling, structured as follows.

a. Apply inverse modeling, for example by using a method such as thatillustrated in Zachary K. Lee, et al., “Two-dimensional Doping ProfileCharacterization of MOSFET's by Inverse Modeling Using I-VCharacteristics in the Subthreshold Region”, IEEE Trans. ElectronDevices, vol. 46, pp. 1640–1649, August 1999, which is incorporated byreference herein in its entirety, to get the two-dimensional profile ofthe initial/nominal structure.

b. Perturb the physical device parameters, for example channel implantsenergy and dose, oxide thickness and the like, of the inverse modeledstructure according to a pre-defined Design Of Experiments (DOE), suchas Central Composite Design

c. Run device simulations. Extract DC and AC device characteristics 155corresponding to each point in the chosen DOE.

An alternative DOE method involves measurement of split lots in silicon.This entails running a set of split lots corresponding to a pre-definedDOE, wherein a set of measurable device characteristics, such as channelimplants dose and energy, are perturbed, and measuring a set of DC andAC device characteristics corresponding to each point of the DOE

A first order expansion of the compact model equations is performed forthe DC and AC measurements performed in step iii as a function of themodel variables.

4. A set of Figure Of Merit circuits is defined.

5. The performance parameters of the FOM circuits are evaluated for allthe points of the DOE defined above and a Response Surface Methodology(RSM) model is constructed.

6. The RSM macro-models are optimized according to a set of performanceobjectives and specifications. The AC/DC device characteristics 155corresponding to the optimum are extracted and:

7. The optimal setting of the device architecture parameters is obtainedaccording to one of the two following options.

By directly applying the results of the optimization step (step 146).

By applying inverse modeling as in step 160, to the optimized AC/DCdevice characteristics 155, the resulting optimal 2-D device profile 165is obtained.

EXAMPLE

This co-design methodology has been applied to improve the analogcharacteristics of transistors from an advanced 120 nm CMOS logictechnology. Analog performances were monitored using operationaltransconductance amplifiers (OTAs), current mirrors and MOS switches.Digital performances were monitored using multiple fan-out ringoscillators. The objective of the optimization was to improve leakageand output conductance while maintaining speed (i.e. reduce g_(ds),while maintaining t_(pd)). Table 1 compares both the device level andcircuit level performances of the initial and optimized technologies.

Note the 10–15% reduction in g_(ds), and reduction of I_(off) to bringit within the 1 nA/μm requirement. This was achieved by only a 3%increase in t_(pd). It was found that the

TABLE 1 Circuit/ Device Parameter Initial Optim. % NMOS Vtsat (mV) 268286 +7% Vtlin (mV) 400 397 −1% Idsat (μA/μm) 692 673 −3% Ioff (nA/μm)1.43 0.877 −40% gdsmin (μΩ-1) 88.6 7.86 −11% PMOS Vtsat (mV) 215 250+16% Vtlin (mV) 404 440 +9% Idsat (μA/μm) 340 327 −3% Ioff (nA/μm) 1.460.49 −66% gdsmin (μΩ-1) 96.3 82.6 −15% Ring tpd (psec) 16.7 17.3 +3%Osc. OTA (p- Av (dB) 35.7 33.4 −7% load) f3db (KHz) 363 474 +30% Pwr(μW) 1.19 1.13 −5% OTA (n- Av (dB) 33.7 33.13 −2% load) f3db (KHz) 254.5269.5 +6% Pwr (μW) 1.22 1.22 0%optimized device characteristics could be achieved by adjusting thepocket doping profile of both devices. The net effect of those changeswas to make the pocket profile more retrograde in both cases. No otherchanges to the device structures were required.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the invention which may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

1. A method for selecting a process for forming a device, comprising:(a) generating a plurality of equations using a response surfacemethodology model, each equation relating a respective device simulatorinput parameter to a respective combination of processing parametersthat can be used to form the device, the plurality of equationsincluding an equation for each respective simulator input parameter; (b)forming a model of electrical performance of a figure-of-merit circuitthat is representative of an integrated circuit into which the device isto be incorporated; and (c) identifying one of the combinations ofprocessing parameters that results in a device having electricalperformance satisfying a set of performance specifications for thefigure-of-merit circuit, using the plurality of equations and the devicesimulator.
 2. The method of claim 1, wherein the device simulator is aprocessor executing a SPICE program.
 3. The method of claim 2, whereinstep (a) includes identifying variations in a plurality ofcharacteristics of the device based on simulation or experimentalmeasurement of respective combinations of processing parameters in adesign of experiment (DOE).
 4. The method of claim 3, wherein step (a)further includes extracting a respective set of device model parametersfor each of the combinations of the processing parameters in the DOE. 5.The method of claim 4, wherein step (a) further includes fitting arespective polynomial model to each respective set of device modelparameters, to form respective ones of the plurality of equations.
 6. Amethod for optimizing a design of a device, comprising the steps of: (a)identifying variations in a plurality of characteristics of the devicebased on simulation or experimental measurement of respectivecombinations of processing parameters in a design of experiment (DOE);(b) extracting a respective set of device model parameters for each ofthe combinations of the processing parameters in the DOE; (c) fitting arespective polynomial model to each respective set of device modelparameters, to form respective equations, each equation outputting aSPICE input parameter; (d) selecting a figure-of-merit circuit havingelectrical characteristics representative of an integrated circuit intowhich the device is to be incorporated; and (e) identifying one of thecombinations of processing parameters that satisfies a set ofperformance specifications for the figure-of-merit circuit, using thepolynomial models and SPICE.
 7. The method of claim 6, furthercomprising the steps of: (f) simulating or measuring a further pluralityof characteristics of the device based on the identified combination ofprocessing parameters of step (e); and (g) performing inverse modelingto identify a final device structure.
 8. The method of claim 7, furthercomprising: (h) developing an initial device structure based on thecharacteristics of the device identified in step (a); and (i) comparingthe final device structure to the initial device structure.
 9. Themethod of claim 6, wherein step (e) includes running a respective SPICEsimulation for each of the combinations of processing parameters.
 10. Amethod for designing a device, comprising: (a) generating a plurality ofequations using a response surface methodology model, each equationrelating a respective device simulator input parameter to a respectivecombination of device characteristics, the plurality of equationsincluding an equation for each respective simulator input parameter; (b)forming a model of electrical performance of a figure-of-merit circuitthat is representative of an integrated circuit into which the device isto be incorporated; and (c) identifying one of the combinations ofdevice characteristics that causes the device to satisfy a set ofelectrical performance specifications for the figure-of-merit circuit,using the plurality of equations and the device simulator.
 11. Themethod of claim 10, wherein the device simulator is a processorexecuting a SPICE program.
 12. The method of claim 11, wherein step (a)includes identifying variations in a plurality of characteristics of thedevice based on simulation or experimental measurement of respectivecombinations of processing parameters in a design of experiment (DOE).13. The method of claim 12, wherein step (a) further includes extractinga respective set of device model parameters for each of the combinationsof the processing parameters in the DOE.
 14. The method of claim 13,wherein step (a) further includes fitting a respective polynomial modelto each respective set of device model parameters, to form respectiveones of the plurality of equations.
 15. A system for selecting a processfor forming a device, comprising: means for generating a plurality ofequations using a response surface methodology model, each equationrelating a respective device simulator input parameter to a respectivecombination of processing parameters that can be used to form thedevice, the plurality of equations including an equation for eachrespective simulator input parameter; means for forming a model ofelectrical performance of a figure-of-merit circuit that isrepresentative of an integrated circuit into which the device is to beincorporated; and means for identifying one of the combinations ofprocessing parameters that results in causing the device to satisfy aset of electrical performance specifications for the figure-of-meritcircuit, using the plurality of equations and the device simulator. 16.A system for designing a device, comprising: means for generating aplurality of equations using a response surface methodology model, eachequation relating a respective device simulator input parameter to arespective combination of device characteristics, the plurality ofequations including an equation for each respective simulator inputparameter; means for forming a model of electrical performance of afigure-of-merit circuit that is representative of an integrated circuitinto which the device is to be incorporated; and means for identifyingone of the combinations of device characteristics that satisfies a setof electrical performance specifications for the figure-of-meritcircuit, using the plurality of equations and the device simulator.